1. Field of the Invention
The present invention relates to a shallow trench isolation method for a semiconductor wafer.
2. Description of the Prior Art
Each MOS transistor component on a semiconductor wafer must be well isolated from neighboring components to prevent interference or short circuiting. In general, localized oxidation isolation (LOCOS) and shallow trench isolation methods are used for isolating the MOS transistors within the semiconductor wafer. Using the LOCOS method a SiO2 layer (field oxide layer) is formed with an intra-transistor distance of several thousand angstroms by oxidizing the Si substrate of a semiconductor wafer at a high temperature. However, there are always crystal defects associated with generating a field oxide layer with the LOCOS method which include a bird's beak deformity that can affect neighboring components and destroy the integrity of the integrated circuit.
At present, the most commonly used isolation method for isolating MOS transistors in semiconductor processing less than 0.25 μm is shallow trench isolation. Although this method effectively achieves electrical isolation by filling dielectric material in the shallow trench between any two neighboring components within the semiconductor wafer, there is still a possibility of the “dishing” phenomenon occurring on the surface of shallow trench. This may affect the electrical performance of the semiconductor wafer. Please refer to FIGS. 1 to 6. FIGS. 1 to 6 show the prior art shallow trench isolation method for a semiconductor wafer. As shown in FIG. 1, a semiconductor wafer 10 comprises a Si substrate 14, a pad oxide layer 16 formed over the Si substrate 14, and a pad nitride layer 18 deposited above the pad oxide layer 16. The pad oxide layer 16 and pad nitride layer 18 are used as a mask or sacrificial layer during the ion implantation or heat diffusion process which is followed by photolithography and etching to form a plurality of shallow trenches 12 on the surface of the semiconductor wafer 10.
Afterwards, chemical vapor deposition (CVD) is performed to deposit a Si(OC2H5)4 (tetra-ethyl-ortho-silicate TEOS) layer and a Poly-Silicon layer in the proper order. As shown in FIG. 2, the TEOS layer 20 covers the entire surface of the semiconductor wafer 10 and is used as a dielectric layer, and the Poly-Silicon layer 22 is used as a mask.
At this point, the unnecessary parts of the Poly-Silicon layer 22 are eliminated and the surface of the semiconductor wafer 10 is polished by chemical mechanical polishing (CMP). As shown in FIG. 3, the Poly-Silicon 24 in the overlying dishes above the corresponding shallow trenches 12 remain. This makes the surface of the semiconductor wafer 10 flat.
Please refer to FIG. 4. The Poly-Silicon 24 and TEOS layer 20 remaining on the surface of the semiconductor wafer 10 is etched with reactive ion etching or magnetically enhanced reactive ion etching techniques. The Poly-Silicon 24 remaining after this procedure serves as a mask over the shallow trench 12. After etching, several remaining overhangs 26 are formed above the shallow trenches 12. The remaining TEOS layer 20 and several overhangs 26 are then adjusted to form a tighter structure of solid SiO2.
CMP is performed to eliminate the remaining overhangs 26 and to polish the surface of the semiconductor wafer 10 making it flat as shown in FIG. 5. Finally, the pad oxide layer 16 and pad nitride layer 18 are stripped by etching. As shown in FIG. 6, only Si substrate 14 and several shallow trenches 12 of TEOS remain on the surface of semiconductor wafer 10.
When performing CMP and back etching shown in FIG. 5 and FIG. 6, the overhangs 26 do not work perfectly as masks; therefore, the surface of TEOS in the shallow trench 12 becomes etched. If the shallow trench 12 is big, the surface of TEOS etched is big, and a dish 28 is generated on the surface. The wider the surface, the more severe the dishing which can affect the semiconductor wafer 10. Also, when depositing the film layer, a focusing problem will occur when transferring patterns.